- 目錄
第1篇 高級ic驗(yàn)證工程師崗位職責(zé)任職要求
高級ic驗(yàn)證工程師崗位職責(zé)
ic驗(yàn)證高級工程師 采微科技 上海采微電子科技有限公司 1.?develop test plans, tests and verification infrastructure for comple_ ip's/sub-system/soc's
2.?create verification environment for both directed and random verification
3.?create reusable bus functional models, monitors, checkers and scoreboards
4.?drive functional coverage driven verification closure
5.?work with architects, designers and post-silicon teams
任職條件
1.?ms with 5+ or 3+ years of e_perience in design verification
2.?e_perience with risc cpu (riscv/mips/arm) related ips verification are highly desirable
3.?e_perience with usb/mipi_csi/mipi_dsi or other high speed interface ips verification are highly desirable
4.?e_perience with deep learning accelerator related ips verification are highly desirable
5.?e_cellent knowledge of popular eda simulation tools (vcs or equivalent simulation tools, debug tools like debussy, simvision)
6.?e_perience in system verilog or similar hvl is highly desirable
7.?c++ programming language e_perience desirable
8.?scripting knowledge (perl/shell)
9.?e_cellent communication skills and ability to lead highly competent team.
高級ic驗(yàn)證工程師崗位
第2篇 ic驗(yàn)證工程師職位描述與崗位職責(zé)任職要求
職位描述:
1. 工作內(nèi)容:
a)負(fù)責(zé)芯片或ip的驗(yàn)證相關(guān)工作;
b)驗(yàn)證環(huán)境和相關(guān)腳本的開發(fā)和維護(hù);
c)與設(shè)計(jì)人員合作,協(xié)調(diào)驗(yàn)證的相關(guān)工作;
2.崗位需求:
a)碩士學(xué)歷,3到5年工作經(jīng)驗(yàn);
b)精通systemverilog和uvm驗(yàn)證方法學(xué);
c)熟悉相關(guān)eda工具;
d)有soc層次驗(yàn)證環(huán)境開發(fā)經(jīng)驗(yàn)優(yōu)先。
第3篇 ic驗(yàn)證崗位職責(zé)任職要求
ic驗(yàn)證崗位職責(zé)
工作內(nèi)容:
a) 負(fù)責(zé)芯片或ip的驗(yàn)證相關(guān)工作;
b) 驗(yàn)證環(huán)境和相關(guān)腳本的開發(fā)和維護(hù);
c) 與設(shè)計(jì)人員合作,協(xié)調(diào)驗(yàn)證的相關(guān)工作;
2. 崗位需求:
a) 碩士學(xué)歷,3到5年工作經(jīng)驗(yàn);
b) 精通systemverilog和uvm驗(yàn)證方法學(xué);
c) 熟悉相關(guān)eda工具;
d) 有soc層次驗(yàn)證環(huán)境開發(fā)經(jīng)驗(yàn)優(yōu)先。
ic驗(yàn)證崗位
第4篇 高級asic驗(yàn)證工程師職位描述與崗位職責(zé)任職要求
職位描述:
崗位職責(zé):
搭建模塊級和系統(tǒng)級uvm驗(yàn)證環(huán)境
根據(jù)設(shè)計(jì)需求文檔制定模塊級和系統(tǒng)級驗(yàn)證方案,跟設(shè)計(jì)工程師一起審查設(shè)計(jì)和驗(yàn)證
驗(yàn)證整個(gè)設(shè)計(jì),調(diào)試各種錯(cuò)誤與設(shè)計(jì)中的bug
管理驗(yàn)證的審查,建立代碼質(zhì)量的標(biāo)準(zhǔn)
崗位要求:
碩士及以上學(xué)歷,三年以上相關(guān)工作經(jīng)驗(yàn)
精通verilog,systemverilog,sva及腳本語言(perl, shell等)
精通uvm驗(yàn)證的工具和環(huán)境
有視頻編解碼,圖像處理和外設(shè)(mipi、usb,存儲控制器等)調(diào)試經(jīng)驗(yàn)者優(yōu)先
具有較強(qiáng)的溝通、學(xué)習(xí)和撰寫英文文檔的能力
responsibilities:
build system and unit-level uvm verification environment
create system and unit-level verification plans from specification and review with design engineers
debug failures and manage bug tracking
conduct verification reviews and set standard for coding quality
qualifications:
master degree or above, with 3+ years working e_perience
proficiency in system verilog, object oriented programming, scripting languages
e_perience in uvm development a plus
e_perience in debugging designs of video codec, isp and peripherals (mipi, usb, memory controller, etc.) is a plus
e_cellent written, verbal and presentation skills